In the Moonshots episode recorded on 1 September and published on 2 September, the panel stopped its news run-through to watch a launch video. On screen, a Palo Alto startup called Architect Labs was announcing Redwood, which it describes as the first AI chip designed end to end by AI. "We only had a single spec written by two architects," the video says. "Our AI took it from an idea to silicon-ready design in two weeks."
The host, Peter Diamandis, had introduced it with a longer list: from that specification, he said, the AI system autonomously generated the performance model, the register transfer level design, the verification environment, the firmware, the drivers and the custom compute kernel, "with zero human intervention." His summary was "a chip designed entirely by AI in two weeks, zero bugs on first silicon, and 3.4 times the performance per watt of Nvidia's Jetson."
Before the discussion went further, the interests came out. Alex, who flagged the story, said, "I should add I'm an advisor to architect." A panelist then noted that Architect is also a Link Ventures portfolio company and that Diamandis is in that fund. The reply on the show: "we're all investors in this one. We're all guilty."
What the two weeks produced
Some vocabulary helps here. A register transfer level design, or RTL, is the code that describes what a chip's circuits do, cycle by cycle — the closest thing chip engineering has to source code. Verification is the enormous testing effort that checks that description behaves as intended before anyone spends money turning it into physical silicon. Firmware and kernels are the low-level software that makes the finished part usable.
Architect Labs' paper, posted on 26 August 2026, describes hardware and software generated together from the two architects' specification. It reports two weeks to reach verified RTL, firmware, kernels and deployment on an FPGA, with model inference brought online in a third week. An FPGA is a reconfigurable chip that can be programmed to imitate a design, so engineers can run it on real hardware without manufacturing anything. That is what the video means by "This isn't just a simulation. Redwood is running live on FPGA hardware right now."
The paper reports that every block reached 95% code and functional coverage — a measure of how much of the design the tests exercised — and that no bugs that escaped verification had turned up on the FPGA. Physical design, tapeout (sending the design to a factory) and post-silicon validation are listed as future work. There is no fabricated Redwood chip yet.
What the numbers compare
The efficiency comparison is against NVIDIA's Jetson Orin Nano, a small module used for AI on devices rather than in data centers. Running the small open-weight model Qwen3-0.6B over 128 generated tokens, the FPGA version of Redwood averaged 12.1 tokens per second; the Jetson measured 28.
The 3.4-fold figure is a different comparison. It projects what Redwood would do as a fabricated chip on Samsung's 8-nanometer process: 49 tokens per second at 1.335 watts, against the Jetson's measured 28 tokens per second at 2.59 watts. Both power figures cover compute only, excluding memory controllers and peripherals — parts that, in a shipped product, also draw power.
The "designless" company
For Alex, the shape of the business mattered as much as the benchmark. NVIDIA has been fabless for decades, he said, proud of owning no factories. Architect, he said, calls itself "designless": it prides itself on not having very many designers, which he put forward as the next step after being fabless.
His larger argument is about what happens when Moore's Law — the long run of cheaper, denser transistors — stops delivering. Absent a successor to today's CMOS manufacturing, he said, the remaining way to get performance is "by crushing down the abstraction stack of modern computer architecture": collapsing the separations between models, operating systems, chip design and the underlying physics. One version of that is burning a specific AI model directly into silicon, in what he called "fast fashion style." The video's own framing points the same way: "In the future, every workload that matters will have its own chip."
One of the panelists put the compounding case in household terms. A laptop with a four-gigahertz processor and 32 cores grinding away produces "an Excel spreadsheet that's no better than it was 20 years ago," the panelist said, because the layers of abstraction between them are so inefficient. If AI can write code at the microcode level and design the chip to fit the task, the argument went, "you're unlocking probably seven layers of factor of 10 in efficiency that are all compounding" — loose arithmetic for "a million X kind of performance gains everywhere." The panel's summary was that improvement is now happening at the model layer and the chip layer at once, and "these don't add, they multiply."
The data question, and NVIDIA's own model
Asked why NVIDIA had not done this first, Dave said they are certainly doing it internally, and that the interesting part is where anyone gets the raw material. This is one of many businesses where "if you can get the data, you can just crush it," he said, "because chip design data is incredibly closely held, guarded secret material." On his account, Architect got there early enough to partner with chip design companies outside NVIDIA, train a proprietary model, and start a flywheel in which being on the map brings more data.
That led him to the acquisition question: "does Jensen pay $5, $10, $20 billion?" He reached for General Electric buying up light bulb patents as the historical rhyme, and did the sums on why it might be worth it — NVIDIA's chief executive is "making, no joke, a billion dollars a day," so "if he can stretch the lifespan of NVIDIA by a week, that's $7 billion." Asked directly whether this threatens NVIDIA, the answer on the show was "Yeah, absolutely," with the alternative that AMD or someone else buys it to close the gap.
A panelist added a comparison that had not yet come up. NVIDIA announced its own chip-design foundation model, ChipNeMo, a few years ago, trained in part on Verilog, and "to my knowledge, they never made it generally available." NVIDIA's October 2023 announcement presents ChipNeMo as an internal assistant customized on company design data, with initial uses narrower than designing a chip: answering questions about technical documents, generating short scripts for design software, and keeping bug descriptions up to date, the last of which NVIDIA reported was received especially favorably. The customization example used roughly 24 billion tokens of internal data followed by about 130,000 conversation and design examples. The stated ambition was help across more stages of chip development. As that panelist saw it, the gap left in the market is "radically democratizing the ability to use AI to design chips for more AI."
That is the loop Architect is advertising. Its video claims each architectural iteration is designed, verified and validated in the lab within 48 hours, and the paper reports that the Qwen model running on Redwood contributed timing and kernel improvements used in subsequent designs. The next iteration of that loop still has to pass through a factory.
The discussion appears in Moonshots with Peter Diamandis, episode 285.